Data pack structure

ABSTRACT

A bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is coupled between the second bus and the link. The first interface and the second interface are operable to (a) send information serially through the link in a format different from that of the first bus and the second bus, (b) approve an initial exchange between the first bus and the second bus in response to pending transactions having a characteristic signifying a destination across the bridge, (c) exchange information between the first bus and the second bus according to a predetermined hierarchy giving the first bus a higher level than the second bus, and (d) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus, including memory devices and input/output devices that may be present: (i) using on the first bus substantially the same type of addressing as is used to access devices the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to data processing systems, andmore particularly, to bridge systems including mechanisms fortransferring information between buses.

[0003] 2. Description of Related Art

[0004] Computers can use buses to transfer data between a host processorand various devices, such as memory devices and input/output devices. Asused herein an “input/output” device is a device that either generatesan input or receives an output (or does both). Thus “input/output” isused in the disjunctive. These buses may be arranged in a hierarchy withthe host processor connected to a high level bus reserved for exchangingthe data most urgently needed by the processor. Lower level buses mayconnect to devices having a lower priority.

[0005] Other reasons exist for providing separate buses. Placing anexcessive number of devices on one bus produces high loading. Suchloading makes a bus difficult to drive because of the power needed andthe delays caused by signaling so many devices. Also, some devices on abus may periodically act as a master and request control over a bus inorder to communicate with a slave device. By segregating some devices ona separate bus, master devices can communicate with other devices on thelower level bus without tying up the bus used by the host processor orother masters.

[0006] The PCI bus standard is specified by the PCI Special InterestGroup of Hillsboro, Oreg. The PCI bus features a 32-bit wide,multiplexed address-data (AD) Maintaining a high data throughput rate(e.g., a 33 MHZ clock rate) on the PCI bus leads to a fixed limitationon the number of electrical AC and DC loads on the bus. Speedconsiderations also limit the physical length of the bus and thecapacitance that can be placed on the bus by the loads, while future PCIbus rates (e.g., 66 MHZ) will exacerbate the electrical load andcapacitance concerns. Failure to observe these load restrictions cancause propagation delays and unsynchronized operation between busdevices.

[0007] To circumvent these loading restrictions, the PCI bus standardspecifies a bridge to allow a primary PCI bus to communicate with asecondary PCI bus through such a bridge. Additional loads may be placedon the secondary bus without increasing the loading on the primary bus.For bridges of various types see U.S. Pat. No. 5,548,730 and 5,694,556.

[0008] The PCI bridge observes a hierarchy that allows an initiator orbus master on either bus to complete a transaction with a target on theother bus. As used herein, hierarchy refers to a system for which theconcept of a higher or lower level has meaning. For example, a PCI bussystem is hierarchical on several scores. An ordering of levels isobserved in that a high level host processor normally communicates froma higher level bus through a bridge to a lower level bus. An ordering oflevels is also observed in that buses at equal levels do not communicatedirectly but through bridges interconnected by a higher level bus. Also,an ordering of levels is observed in that data is filtered by theiraddresses before being allowed to pass through a bridge, based on thelevels involved. Other hierarchical systems exist that may observe anordering of levels by using one or more of the foregoing concepts, or byusing different concepts.

[0009] Some personal computers have slots for add-on cards. Because auser often needs additional slots, expansion cards have been designedthat will connect between the peripheral bus and an external unit thatoffers additional slots for add-on cards. For systems for expanding abus, see U.S. Pat. Nos. 5,006,981; 5,191,657; and 5,335,329. See alsoU.S. Pat. No. 5,524,252.

[0010] For portable computers, special considerations arise when theuser wishes to connect additional peripheral devices. Often a user willbring a portable computer to a desktop and connect through a dockingstation or port replicator to a keyboard, monitor, printer or the like.A user may also wish to connect to a network through a network interfacecard in the docking station. At times, a user may need additionaldevices such as hard drives or CD-ROM drives. While technically possibleto a limited extent, extending a bus from a portable computer through acable is difficult because of the large number of wires needed andbecause of latencies caused by a cable of any significant length.

[0011] In U.S. Pat. No. 5,696,949 a host chassis has a PCI to PCI bridgethat connects through a cabled bus to another PCI to PCI bridge in anexpansion chassis. This system is relatively complicated since twoindependent bridges communicate over a cabled bus. This cabled busincludes essentially all of the lines normally found in a PCI bus. Thisapproach employs a delay technique to deal with clock latenciesassociated with the cabled bus. A clock signal generated on theexpansion side of the cabled bus: (a) is sent across the cabled bus, butexperiences a delay commensurate with the cable length; and (b) isdelayed an equivalent amount on the expansion side of the cabled bus bya delay line there, before being used on the expansion side. Such adesign complicates the system and limits it to a tuned cable of apre-designed length, making it difficult to accommodate work spaces withvarious physical layouts.

[0012] U.S. Pat. No. 5,590,377 shows a primary PCI bus in a portablecomputer being connected to a PCI to PCI bridge in a docking station.When docked, the primary and secondary buses are physically very close.A cable is not used to allow separation between the docking station andthe portable computer. With this arrangement, there is no interfacecircuitry between the primary PCI bus and the docking station. See alsoU.S. Pat. No 5,724,529.

[0013] U.S. Pat. No. 5,540,597 suggests avoiding additional PCMCIAconnectors when connecting a peripheral device to a PC card slot in aportable computer, but does not otherwise disclose any relevant bridgingtechniques.

[0014] U.S. Pat. No. 4,882,702 and show a programmable controller forcontrolling industrial machines and processes. The system exchanges dataserially with a variety of input/output modules. One of these modulesmay be replaced with an expansion module that can serially communicatewith several groups of additional input/output modules. This system isnot bridge-like in that the manner of communicating with the expansionmodule is different than the manner of communicating with theinput/output modules. For the expansion module the system changes to ablock transfer mode where a group of status bytes are transferred forall the expansion devices. This system is also limited to input/outputtransactions and does not support a variety of addressable memorytransactions. See also U.S. Pat. Nos. 4,413,319; and 4,504,927.

[0015] In U.S. Pat. No. 5,572,525 another bus designed forinstrumentation (IEEE 488 General Purpose Instrumentation Bus) connectsto an extender that breaks the bus information into packets that aresent serially through a transmission cable to another extender. Thisother extender reconstructs the serial packets into parallel data thatis applied to a second instrumentation bus. This extender is anintelligent system operating through a message interpretation layer andseveral other layers before reaching the parallel to serial conversionlayer. Thus this system is unlike a bridge. This system is also limitedin the type of transactions that it can perform. See also U.S. Pat. No.4,959,833.

[0016] U.S. Pat. No. 5,325,491 shows a system for interfacing a localpus to a cable with a large number of wires for interfacing with remoteperipherals. See also U.S. Pat. Nos. 3,800,097; 4,787,029; 4,961,140;and 5,430,847.

[0017] The Small Computer System Interface (SCSI) defines bus standardsfor a variety of peripheral devices. This CSI bus is part of anintelligent system that responds to high-level commands. Consequently,SCSI systems require software drivers to enable hardware to communicateto the SCSI bus. This fairly complicated system is quite different frombridges such as bridges as specified under the PCI standard. A varietyof other complex techniques and protocols exist for transferring data,including Ethernet, Token Ring, TCP/IP, ISDN, FDDI, HIPPI, ATM, FibreChannel, etc., but these bear little relation to bridge technology.

[0018] See also U.S. Pat. Nos. 4,954,94915,038,320; 5,111,423;5,446,869; 5,495,569; 5,497,498; 5,507,002; 5,517,623; 5,530,895;5,542,055; 5,555,510; 5,572,688; and 5,611,053.

[0019] Accordingly, there is a need for an improved system fortransferring information between buses.

SUMMARY OF THE INVENTION

[0020] In accordance with the illustrative embodiments demonstratingfeatures, and advantages of the present invention, there is provided abridge accessible by a host processor for expanding access over a firstbus to a second bus. The first bus and the second bus are each adaptedto separately connect to respective ones of a plurality ofbus-compatible devices. Allowable ones of the devices include memorydevices and input/output devices. The bridge has a link, together with afirst and a second interface. The second interface is adapted to couplebetween the second bus and the link. The first interface and the secondinterface operating as a single bridge are operable to (a) send outgoinginformation serially through the link in a format different from that ofthe first bus and the second bus without waiting for an incomingacknowledgment over said link before inaugurating a transfer of saidinformation over said link, (b) approve an initial exchange between thefirst bus and the second bus in response to a pending transaction havinga characteristic signifying a destination across the bridge, and (c)allow the host processor, communicating through the first bus, toindividually address different selectable ones of the bus-compatibledevices on the second bus, including memory devices and input/outputdevices that may be present: (i) using on the first bus substantiallythe same type of addressing as is used to access devices the first bus,and (ii) without first employing a second, intervening one of thebus-compatible devices on the second bus.

[0021] In accordance with another aspect of the invention a bridgeaccessible by a host processor can expand access over a first bus to asecond bus. The first bus and the second bus each are adapted toseparately connect to respective ones of a plurality of bus-compatibledevices. Allowable ones of the devices include memory devices andinput/output devices. The bridge has a link, together with a first and asecond interface. The first interface is adapted to couple between thefirst bus and the link. The second interface is adapted to couplebetween the second bus and the link. The first interface and the secondinterface are operable to (a) send information serially through the linkin a format different from that of the first bus and the second bus, (b)exchange information between the first bus and the second bus accordingto a predetermined hierarchy giving the first bus a higher level thanthe second bus, and (c) allow the host processor, communicating throughthe first bus, to individually address different selectable ones of thebus-compatible devices on the second bus, including memory devices andinput/output devices that may be present: (i) using on the first bussubstantially the same type of addressing as is used to access deviceson the first bus, (ii) without first employing a second intervening oneof the bus-compatible devices on the second bus, and (iii) withoutpassing the information through an intervening hierarchical level.

[0022] In accordance with another, further aspect of the invention abridge accessible by a processor can expand access over a first bus to asecond bus. The first bus and the second bus each are adapted toseparately connect to respective ones of a plurality of bus-compatibledevices. The bridge has a link and a first and a second interface. Thefirst interface is coupled between the first bus and the link. Thesecond interface is adapted to couple between the second bus and thelink. The first interface and the second interface operate as a singlebridge and is operable to transfer information serially through the linkin a format different from that of the first bus and the second buswithout waiting for an incoming acknowledgment over the link beforeinaugurating a transfer of the information over the link.

[0023] By employing apparatus and methods of the foregoing type, animproved system is achieved for transferring information between buses.In one preferred embodiment, two buses communicate over a duplex linkformed with a pair of simplex links, each employing twisted pair or twinaxial lines (depending on the desired speed and the anticipatedtransmission distance). Information from the buses are first loaded ontoFIFO (first-in first-out) registers before being serialized into framesfor transmission over the link. Received frames are deserialized andloaded into FIFO registers before being placed onto the destination bus.Preferably, interrupts, error signals, and status signals are sent alongthe link.

[0024] In this preferred embodiment, address and data are taken from abus one transaction at a time, together with four bits that act eitheras control or byte enable signals. Two or more additional bits may beadded to tag each transaction as either: an addressing cycle;acknowledgment of a non-posted write; data burst; end of data burst (orsingle cycle). If these transactions are posted writes they can berapidly stored in a FIFO register before being encoded into a number offrames that are sent serially over a link. When pre-fetched reads areallowed, the FIFO register can store pre-fetched data in case theinitiator requests it. For single cycle writes or other transactionsthat must await a response, the bridge can immediately signal theinitiator to wait, even before the request is passed to the target.

[0025] In a preferred embodiment, one or more of the buses follows thePCI or PCMCIA bus standard (although other bus standards can be usedinstead). The preferred apparatus then operates as a bridge with aconfiguration register that is loaded with information specified un erthe PCI standard. The apparatus can transfer information between busesdepending upon whether the pending addresses fall within a rangeembraced by the configuration registers. This scheme works with deviceson the other side of the bridge, which can be given unique baseaddresses to avoid addressing conflicts.

[0026] In one highly preferred embodiment, the apparatus maybe formed astwo separate application-specific integrated circuits (ASIC) joined by acable. Preferably, these two integrated circuits have the samestructure, but can act in two different modes in response to a controlsignal applied to one of its pins. Working with hierarchical buses(primary and secondary buses) these integrated circuits will be placedin a mode appropriate for its associated bus. The ASIC associated withthe secondary bus preferably has an arbiter that can grant masterscontrol of the secondary bus. This preferred ASIC can also supply anumber of ports to support a mouse an keyboard, as well as parallel andserial ports.

[0027] When used with a portable computer, one of the ASIC's can beassembled with a connector in a package designed to fit into a PC cardslot following the PCMCIA standard. This ASIC can connect through acable to the other ASIC, which can be located in a docking station.Accordingly, the apparatus can act as a bridge between a CardBus and aPCI bus located in a docking station. Since the preferred ASIC can alsoprovide a port for a mouse and keyboard, this design is especiallyuseful for a docking station. Also, the secondary PCI bus implemented bythe ASIC can connect to a video card or to a video processing circuit onthe main dock circuit board in order to drive a monitor.

[0028] In some embodiments, one ASIC will be mounted in the portablecomputer by the original equipment manufacturer (OEM). This portablecomputer will have a special connector dedicated to the cable thatconnects to the docking station with the mating ASIC. For suchembodiments, the existence within the preferred ASIC of ports forvarious devices can be highly advantageous. An OEM can use this alreadyexisting feature of the ASIC and thereby eliminate circuitry that wouldotherwise have been needed to implement such ports.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above brief description as well as other objects, featuresand advantages of the present invention will be more fully appreciatedby reference to the following detailed description of presentlypreferred but nonetheless illustrative embodiments in accordance withthe present invention when taken in conjunction with the accompanyingdrawings, wherein:

[0030]FIG. 1 is a schematic block diagram showing a bridge split by alink within the bridge, in accordance with principles of the presentinvention;

[0031]FIG. 2 is a schematic block diagram showing a bridge in accordancewith principles of the present invention using the link of FIG. 1;

[0032]FIG. 3 is a schematic block diagram showing the bridge of FIG. 2used in a docking system in accordance with principles of the presentinvention;

[0033]FIG. 4 is a cross-sectional view of the cable of FIG. 3;

[0034]FIG. 5 is a schematic illustration of the bridge of FIG. 3 shownconnected to a portable computer and a variety of peripheral devices;and

[0035]FIG. 6 shows a docking station similar to that of FIG. 5 but withthe portable computer modified to contain an application-specificintegrated circuit designed to support a link to the docking station.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Referring to FIG. 1, a bridge is shown connecting between a firstbus 10 and a second bus 12 (also referred to as primary bus 10 andsecondary bus 12). These buses may be PCI or PCMCIA 32-bit buses,although other types of buses are contemplated and the presentdisclosure is not restricted to any specific type of bus. Buses of thistype will normally have address and data lines. In some cases, such aswit the PCI bus, address and data are multiplexed onto the same lines.In adition, these buses will have signaling lines for allowing deviceson the bus to negotiate transactions. For the PCI standard, thesesignaling lines will in lude four lines that are used either for controlor byte enabling (C/BE[3:01). Others signaling lines under the PCIstandard exist for gaining control over the bus, for handshaking, andthe like (e.g., FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, etc.)

[0037] Buses 10 and 12 are shown connecting to a first interface 14 andsecond interface 16, respectively (also referred to as interfaces 14 and16). Bus information selected for transmission by interfaces 14 and 16are loaded into registers 18 and 20, respectively. Incoming businformation that interfaces 14 and 16 select for submission to the busesare taken from registers 22 and 24, respectively. In one embodiment,registers 18-24 are each 16×38 FIFO registers, although different typesof registers having different dimensions may be used in alternateembodiments.

[0038] In this embodiment, registers 18-24 are at least 38 bits wide.Thirty six of those bits are reserved for the 4 control bits(C/BE#[3:01]) and the 32 address/data bits (AD[31:0]) used under the PCIbus standard. The remaining two bits can be used to send additional tagsfor identifying the nature of the transaction associated therewith.Other bits may be needed to fully characterize every contemplatedtransaction. Transactions can be tagged as: addressing cycle;acknowledgment of a non posted write; data burst; end of data burst (orsingle cycle). Thus outgoing write transactions can be tagged as asingle cycle transaction or as part of a burst. Outgoing read requestscan also be tagged as part of a burst with a sequence of byte enablecodes (C/BE) for each successive read cycle of the burst. It will beappreciated that other coding schemes using a different number of bitscan be use in other embodiments.

[0039] The balance of the structure illustrated in FIG. 1 is a linkdesigned to establish duplex communications between interfaces 14 and 16through registers 18-24. For example, encode 28 can accept the oldest 38bits from register 20 and parse it into five bytes (40 bits). The extratwo bits of the last byte are encoded to signify the interrupts, statussignals and error signals that may be supplied from block 34.

[0040] Each of these five bytes is converted into a 10 bit frame thatcan carry the information of each byte, as well as information usefulfor regulating the link. For example, these frames can carry commamarkers, idle markers, or flow control signals, in a well-known fashion.A transceiver system working with bytes that were encoded into such 10bit frames is sold commercially by Hewlett Packard as model numberHDMP-1636 or-1646. Frames produced by encoder 28 are forwarded throughtransmitter 44 along simplex link 46 to receiver 48, which supplies theserial information to decoder 30. Likewise, encoder 26 forwards serialinformation through transmitter 38 along simplex link 40 to receiver 42,which supplies the serial information to decoder 32.

[0041] Flow control may be necessary should FIFO registers 22 or 24 bein danger of overflowing. For example, if FIFO register 22 is almostfull, it supplies a threshold detect signal 36 to encoder 26, whichforwards this information through link 40 to decoder 32. In response,decoder 32 issues a threshold stop signal 50 to encoder 28, which thenstops forwarding serial information, thereby preventing an overflow inFIFO register 22. In a similar fashion, a potential overflow in FIFOregister 24 causes a threshold detect signal 52 to flow through encoder28 and link 46 to cause decoder 30 to issue a threshold stop signal 54,to stop encoder 26 from sending more frames of information. In someembodiments, the system will examine the received information todetermine if it contains transmission errors or has been corrupted insome fashion. In such event the system can request a retransmission ofthe corrupted information and thereby ensure a highly reliable link.

[0042] In this embodiment, elements 14, 18, 22, 26, 30, 38 and 48 arepart of a single, application specific integrated circuit (ASIC) 56.Elements 16, 20, 24, 28, 32, 42 and 44 are also part of an ASIC 58. Asdescribed further hereinafter, first ASIC 56 and second ASIC 58 have anidentical structure but can be operated in different mode. It will beappreciated that other embodiments may not use ASIC's but may useinstead alternate circuitry, such as a programable logic device, or thelike. As shown herein, ASIC 56 is operating in a mode designed toservice primary bus 10, and (for reasons to be described presently) willbe sending outputs to block 57. In contrast block 34 of ASIC 58 willreceive inputs from block 34.

[0043] Encoders 26 and 28 have optional parallel outputs 27 and 29,respectively, for applications requiring such information. Also for suchapplications, decoders 30 and 32 have parallel inputs 31 and 33,respectively. These optional inputs and outputs may be connected to anexternal transceiver chip, such as the previously mentioned deviceoffered by Hewlett Packard as model number HDMP-1636 or-1646. Thesedevices will still allow the system to transmit serial information, butby means of an external transceiver chip. This allows the user of theASIC's 56 and 58 more control over the methods of transmission over thelink.

[0044] Referring to FIG. 2, previously mentioned ASIC's 56 and 58 areshown in further detail. The previously mentioned encoders, decoders,transmitters, receivers, and FIFO registers are combined into blocks 60and 62, which are interconnected by a duplex cable formed of previouslymentioned simplex links 40 and 46. Previously mentioned interface 14 isshown connected to primary bus 10, which is also connected to a numberof bus-compatible devices 64. Similarly, previously mentioned interface16 is shown connected to secondary bus 12, which is also connected to anumber of buscompatible devices 66. Devices 64 and 66 may bePCI-compliant devices and may operate as memory devices or input/outputdevices.

[0045] Interface 14 a shown connected to a first register means 68,which acts as a configuration register in compliance with the PCIstandard. Since this system will act as a bridge, configurationregisters 68 will have the information normally associated with abridge. Also, configuration registers 68 will contain a base registerand limit register to indicate a range or predetermined schedule ofaddresses for devices that can be found on the secondary bus 12. Underthe PCI standard, devices on a PCI bus will themselves each have a baseregister, which allows mapping of the memory space and/or I/O space.Consequently, the base and limit registers in configuration registers 68can accommodate the mapping that is being performed by individual PCIdevices. The information on configuration registers 68 are mirrored onsecond configuration register 67 (also referred to as a secondconfiguration means). This makes the configuration information readilyavailable to the interfaces on both sides of the link.

[0046] In this embodiment, ASIC 58 has an arbiter 70. Arbiters are knowndevices that accept requests from masters on secondary bus 12 forcontrol of 25 the bus. The arbiter has a fair algorithm that grants therequest of one of the contending masters by issuing it a grant signal.In this hierarchical scheme, secondary bus 12 requires bus arbitration,but primary bus 10 will provide its own arbitration. Accordingly, ASIC56 is placed in a mode where arbiter 72 is disabled. The modes of ASIC's56 and 58 are set by control signals applied to control pins 74 and 76,respectively. Because of this mode selection, the signal directionsassociated with blocks 57 an 34 will be reversed.

[0047] In this embodiment, ASIC 58 is in a mode that implements a thirdbus 78. Bus 78 may follow the PCI standard, but is more convenientlyimplemented in a different standard. Bus 78 connects to a number ofdevices that act as a port means. For example, devices 80 and 82 canimplement PS/2 ports that 5 can connect to either a mouse or a keyboard.Device 84 implements an ECP/EPP parallel port for driving a printer orother device. Device 86 implements a conventional serial port. Devices80, 82, 84 and 86 are shown with input/output lines 81, 83, 85 and 87,respectively. Devices 80-86 may be addressed on bus 10 as if they werePCI devices on bus 12. Also in this embodiment, a bus 88 is shown inASIC 56, with the same devices as shown on bus 78 to enable an OEM toimplement these ports without the need for separate input/outputcircuits.

[0048] Referring to FIG. 3, previously mentioned ASIC 58 is shown in a15 docking station 130 connected to an oscillator 91 for establishing aremote and internal clock. ASIC 58 has its lines 81 and 83 connectedthrough a connection assembly 90 for connection to a keyboard and mouse,respectively. Serial lines 85 and parallel lines 87 are shown connectedto transceivers 92 and 94, respectively, which then also connect toconnection assembly 90 for connection to various parallel and serialperipheral, such as printers and modems.

[0049] ASIC 58 is also shown connected to previously mentioned secondarybus 12. Bus 12 is shown connected to an a adapter card 96 to allow thePCI bus 12 to communicate with an IDE device such as a hard drive,backup tape drive, CD-ROM drive, etc. Another adapter card 98 is shownfor allowing communications from bus 12 to a universal serial port(USB). A network interface card 100 will allow communications throughbus 12 to various networks operating under the Ethernet standard, TokenRing standard, etc. Video adapter card 102 (also referred to as a videomeans) allows the user to operate another monitor. Add-on card 104 maybe, one of a variety of cards selected by the user to perform a usefulfunction. While this embodiment shows various functions beingimplemented by add-on cards, other embodiments may implement one or moreof these function on a common circuit board in the dock (e.g., allfunctions excluding perhaps the IDE adapter card).

[0050] ASIC 58 communicates through receiver/transmitter 106, whichprovides a physical interface through a terminal connector 108 to cable40, 46. Connector 108 may be a 20 pin connector capable of carrying highspeed signals with EMI shielding (for example a low force helixconnector of the type offered by Molex Incorporated), although otherconnector types may used instead. The opposite end of cable 40, 46connects through a gigabit, terminal connector 110 to physical interface112, which acts as a receiver/transmitter. Interface 112 is shownconnected to previously mentioned first ASIC 56, which is also shownconnected to an oscillator 114 to establish a local clock signal. Thisspecific design contemplates sing an external transmitter/receiver(external SERDES of lines 27, 29, 31, and 33 of FIG. 1), although otherembodiments can eliminate these external devices in favor of theinternal devices in ASIC's 56 and 58.

[0051] This embodiment is adapted to cooperate with a portable computerhaving a PCMCIA 32-bit bus 10, although other types of computers can beserviced. Accordingly, ASIC 56 is shown in a package 116 having anoutline complying with the PCMCIA standard and allowing package 116 tofit into a slot in a portable computer. Therefore, ASIC 56 has aconnector 118 for 25 connection to bus 10. Cable 40, 46 will typicallybe permanently connected to package 116, but a detachable connector maybe used in other embodiments, where a user wishes to leave package 16inside the portable computer.

[0052] Power supply 120 is shown producing a variety of supply voltagesused to power various components. In some embodiments, one of thesesupply lines can be connected directly to the portable computer tocharge its battery. Referring to FIG. 4, the previously mentionedsimplex links 40 and 46 are shown as twin axial lines 40A an 46A,wrapped with individual shields 40B and 46B. A single shield 122encircles the lines 40 and 46. Four parallel wires 124 are shown(although a greater number may be used in other embodiments) mountedaround the periphery of shields 122 for various purposes. These wires124 may carry power management signals, dock control signals or othersignals that may be useful in an interface between a docking station anda portable computer. While twin axial lines offer high performance,twisted pairs or other transmission media may be used in otherembodiments where the transmission distance is not as great and wherethe bit transfer speed need not be as high. While a hard wire connectionis illustrated, in other embodiments a wireless or other type ofconnection can be employed instead.

[0053] Referring to FIG. 5, previously mentioned package 116 is shown inposition to be connected to a PCMCIA slot in portable computer 126.Computer 126 is shown having primary bus 10 and a host processor 128.Package 116 is shown connected through cable 40, 46 to previouslymentioned connector 108 on docking station 130. Previously mentioneddocking station 130 is shown connecting through PS/2 ports to keyboard132 and mouse 134. A printer 136 is shown connected to parallel port indocking station 130. Previously mentioned video means 102 is shownconnected to a monitor 138. Docking station 130 is also shown with aninternal hard drive 140 connecting to the adapter card previouslymentioned. A CD-ROM drive 142 is also shown mounted in docking station130 and connects to the secondary bus through an appropriate adaptercard (not shown). Previously mentioned add-on card 104 is shown with itsown cable 144.

[0054] Referring to FIG. 6, a modified portable computer 126′ is againshown with a host processor 128 and primary bus. In this embodimenthowever, portable computer 126′ contains previously mentioned ASIC 56.Thus there is no circuitry required (other than perhaps drivers) betweenASIC 56 and cable 40, 46. In this case, the laptop end of cable 40, 46has a connector 142 similar to the one on the opposite end of the cable(connector 108 of FIG. 5).Connector 143 is designed to mate withconnector 141 and support the highspeed link. As before, connectors 141and 143 can also carry various power management signals, and othersignal associated with a docking system.

[0055] An important advantage of this arrangement is the fact that ASIC56 contains circuitry for providing ports, such as a serial port, aparallel port, PS12 ports for a mouse and keyboard, and he like. Sinceportable computer 126′ would ordinarily provide such ports, ASIC 56simplifies the design of the portable computer. This advantage is inaddition to the advantage of having a single ASIC design (that is,ASIC's 56 and 58 are structured identically), which single design iscapable of operating at either the portable computer or the dockingstation, thereby simplifying the ASIC design and reducing stockingrequirements, etc.

[0056] To facilitate an understanding of the principles associated withthe foregoing apparatus, its operation will be briefly described. Thisoperation will be described in connection with the docking system ofFIGS. 3 and 5 (which20 generally relates to FIG. 2), although operationwould be similar for other types of arrangements. For the dockingsystem, a connection is established by plugging package 116 (FIG. 5)into portable computer 126. This establishes a link between the primarybus 10 and SIC 56 (FIG. 3).

[0057] At this time an initiator (the host processor or a master) havingaccess to primary bus 10 may assert control of the bus. An initiatorwill normally send a request signal to an internal arbiter (not shown)that will eventually grant control to this initiator. In any event, theinitiator asserting control over primary bus 10 will exchange theappropriate handshaking signals and drive an address onto the bus 10.Control signals simultaneously applied to the signaling lines of bus 10will indicate whether the transaction is a read, write, or other type oftransaction.

[0058] Interface 14 (FIG. 2) will examine the pending address anddetermine whether it represents a transaction with devices on the otherside of the bridge (that is, secondary bus 12) or with the bridgeitself. Configuration register 68 has already been loaded in the usualmanner with information that indicates a range of addresses defining thejurisdiction of the interface 14.

[0059] Assuming a write transaction is pending on bus 10, interface 14will transfer 32 address bits together with four control bits (PCIstandard) to FIFO register 18 (FIG. 1). Encoder 26 will add at least twoadditional bits tagging this information as an addressing cycle. Theinformation is then broken into frames that can carry flow control andother signals before being transmitted serially over link 40.

[0060] Without waiting, interface 14 will proceed to a data cycle andaccept up to 32 bits of data from bus 10 together with four byte enablebits. As before, this information will be tagged, supplemented withadditional information and broken into frames for serial transmissionover link 40. This transmitted information will be tagged to indicatewhether it is part of a burst or a single cycle.

[0061] Upon receipt, decoder 32 restore the frames into the original 38bit format and loads the last two described cycles onto the stack ofregister 24. Interface 16 eventually notices the first cycle as anaddressing cycle in a write request. Interface 16 then negotiatescontrol over bus 12 in the usual fashion and applies the address to bus12. A device on bus 12 will respond to the write request by performingthe usual handshaking.

[0062] Next, interface 16 will drive the rite data stacked on register24 into bus 12. If this transaction is a burst, interface 16 willcontinue to drive data onto bus 12 by fetching it from register 24. Ifhowever this transaction is a single cycle write, interface 16 willclose the transaction on bus 12 and load an acknowledgment into register20. Since this acknowledgment need not carry data or addressinformation, a unique code may be placed into register 20, so thatencoder 28 can appropriately tag this line before parsing it into framesfor transmission over link 46. Upon receipt, decoder 30 will produce aunique code that is loaded into register 22 and eventually forwarded tointerface 14, which sends an acknowledgment to the device on bus 10 thatthe write has 10 succeeded.

[0063] If the initiator instead sets its control bits during the addresscycle to indicate a read request, interface 14 would also accept thiscycle, if it has jurisdiction. Interface 14 will also signal theinitiator on bus 10 that it is not ready to return data (e.g., a retrysignal, which may be the stop signal as defined under the PCI standard).The initiator can still start (but not finish) a data cycle by drivingits signaling lines on bus 10 with byte enable information. Using thesame technique, the address information, followed by the byte enableinformation, will be accepted by interface 14 and loaded with tags intoregister 18. These two lines of information will be then encoded andtransmitted serially 20 over link 40. Upon receipt, this informationwill be loaded into the stack of register 24. Eventually, interface 16will notice the first item as a read request and drive this addressinformation onto secondary bus 12. A device on bus 12 will respond andperform the appropriate handshaking. Interface 16 will then forward thenext item of information from register 24 containing the byte 25enables, onto bus 12 so the target device can respond with the requesteddata. This responsive data is loaded by in 16 into register 20. Ifpre-fetching is indicated, interface 16 will initiate a number ofsuccessive read cycles to accumulate data in register 20 from sequentialaddresses that may or may not be requested by the initiator.

[0064] As before, this data is tagged, broken into frames and sentserially over link 46 to be decoded and loaded into register 22. Thetransmitted data can include pre-fetched data that will be accumulatedin register 22. Interface 14 transfers the first item of returning dataonto primary bus 10, and allows the initiator to proceed to another readcycle if desired. If another read cycle is conducted as part of a bursttransaction, the requested data will already be present in register 22for immediate delivery by interface 14 to bus 10. If these pre-fetcheddata are not requested for the next cycle, then they are discarded.

[0065] Eventually the initiator will relinquish control of bus 10. Next,an initiator 10 on bus 12 may send a request for control of bus 12 toarbiter 70 (FIG. 2). If arbiter 70 grants control, the initiator maymake a read or write request by driving an address onto bus 12.Interface 16 will respond if this address does not fall within thejurisdictional range of addresses specified in configuration register 67(indicating the higher level bus 10 may have jurisdiction). In the samemanner as before, but with a reversed flow over links 40, 46, interface16 may accept address and data cycles and communicate them across link40, 46. Before being granted bus 10, interface 14 will send a request toan arbiter (not shown) associated with bus 10.

[0066] In some instances, an initiator on primary bus 10 will wish toread from, or write to, port means 80, 82, 84, or 86. These four itemsare arranged to act as devices under the PCI standard. Interface 16 willtherefore act as before, except that information will be routed notthrough bus 12, but through bus 78.

[0067] Other types of transactions may be performed, including reads andwrites to the configuration registers 67 and 68 (FIG. 2). Other types oftransactions, as defined under the PCI standard (or other bus standards)may be performed as well.

[0068] Interrupt signals may be generated by the ports or other devicesin ASIC 58. Also external interrupts may be received as indicated byblock 34. As noted before, interrupt signals may be embedded in the codesent over link 46. Upon receipt, system 60 decodes the interrupts andforwards them on to block 57, which may be simply one or more pins fromASIC 56 (implementing, for example, INTA of the PCI standard). Thisinterrupt signal can either be sent over the bus 10 or to an interruptcontroller that forwards interrupts to the host processor. System errorsmay be forwarded in a similar fashion to produce an output on a pin ofASIC 56 that can be routed directly to bus 10 or processed usingdedicated hardware. The designer may wish to send individual statussignals, which can be handled in a similar fashion along link 40, 46.

[0069] It is appreciated that various modifications may be implementedwith respect to the above described, preferred embodiment. In otherembodiments the illustrated ASIC's may be divided into several discretepackages using in some cases commercially available integrated circuits.Also, the media for the link may be wire, fiber-optics, infrared light,radio frequency signals, or other media. In addition, the primary andsecondary buses may each have one or more devices, and these devices maybe in one or more categories, including memory devices and input/outputdevice . Moreover, the devices may operate at a variety of clock speeds,bandwidths and data rates. Furthermore, transactions passing through thebridge may be accumulated as posted writes or as pre-fetched data,although some embodiments will not use such techniques. Also, the bridgedescribed herein can be part of a hierarchy using a plurality of suchbridges having their primary side connected to the same bus or to busesof an equivalent or different level. Additionally, the illustrated ports25 can be of a different number or type, or can be eliminated in someembodiments. Also, the illustrated arbiter can be eliminated forsecondary buses that are not design to be occupied by a master. While asequence of steps is described above, in other embodiments these stepsmay be increased or reduced in number, or performed in a differentorder, without departing from the scope of the present invention.

[0070] Obviously, many modifications an variations of the presentinvention are possible in light of the above teachings It is thereforeto be understood that within the scope of the appended claims, theinvention may be practiced otherwise than as specifically described.

We claim:
 1. A data organization according to a 38-bit coding schemethat enables the expanding a computer system, the coding schemecomprising: 36 reserved bits; and 2 tag bits.
 2. The coding scheme ofclaim 1 wherein the 2 tag bits identify the nature of the transaction.3. The coding scheme of claim 2 wherein the 2 tag bits identify anaddress cycle.
 4. The coding scheme of claim 2 wherein the 2 tag bitsidentify an acknowledgement of a non-posted write.
 5. The coding schemeof claim 2 wherein the 2 tag bits identify a data burst.
 6. The codingscheme of claim 2 wherein the 2 tag bits identify an end of data burst.7. The coding scheme of claim 2 wherein the 2 tag bits identify a singlecycle.
 8. The coding scheme of claim 1 wherein the coding scheme enablesan outgoing write transaction.
 9. The coding scheme of claim 8 whereinthe outgoing write transaction is a single cycle transaction.
 10. Thecoding scheme of claim 8 wherein the outgoing write transaction is partof a burst.
 11. The coding scheme of claim 1 wherein the coding schemeenables an outgoing read request.
 12. The coding scheme of claim 11wherein the outgoing read request is part of a burst.
 13. The codingscheme of claim 12 wherein the part of the burst has a sequence of byteenabled codes for each successive read cycle of the burst.
 14. Aregister containing a data structure organized according to a 38-bitcoding scheme that enables the expanding a computer system, the codingscheme comprising: 36 reserved Pits; and 2 tag bits.
 15. The register ofclaim 14 wherein the data structure comprises an outgoing writetransaction.
 16. The register of claim 14 wherein the data structurecomprises an outgoing read request.
 17. The register of claim 14 whereinthe data structure comprises an outgoing read request as part of a bursthaving a sequence of byte enabled codes for each successive read cycleof the burst.
 18. A means for storing a data structure organizedaccording to a 38-bit coding scheme that enables the expanding acomputer system, the coding scheme comprising: 36 reserved bits; and 2tag bits.
 19. The means of claim 18 wherein the data structure comprisesan outgoing write transaction.
 20. The means of claim 18 wherein thedata structure comprises an outgoing read request.
 21. A dataorganization according to a 40-bit coding scheme that enables theexpanding a computer system, the coding scheme comprising: 36 reservedbits; 2 tag bits; and 2 extra bits.
 22. The data organization of claim21 wherein the 2 extra bits signify an interrupt.
 23. The dataorganization of claim 21 wherein the 2 extra bits signify a statussignal.
 24. The data organization of claim 21 wherein the 2 extra bitssignify an error signal.